The present invention relates to a CAN controller and a one-chip computer having the built-in CAN controller, each of which enables the operation test thereof to be executed stably at a high speed. More particularly, this invention relates to a CAN controller and a one-chip computer having the built-in CAN controller, each of which only when the operation test thereof is performed is prevented from being influenced by the operation of its re-synchronizing function.
With a recent spread of personal computers, establishment of a network build-up technology such as a client server system, and complete arrangement and adjustment of a communication infrastructure, the introduction of a network computing has proceeded not only on an enterprise level but also on a person level. The network computing that is represented by the Internet or a LAN (Local Area Network) in general is mainly intended to perform the exchange of information between people smoothly and over a wide range.
Also, in the field of industry, in a FA (Factory Automation), etc., the pieces of control equipment that have been functionally dispersed and had their dispositions dispersed are conventionally being unitarily controlled and managed by a network to thereby achieve the optimization of the production activity. For example, attention has been drawn toward a CIM (computer integrated manufacturing system) as a computer system that inclusively unifies individual technical data pieces and production data pieces such as a CAD (computer-aided design), CAM (computer-aided design), CAE (computer-aided design), assembling, and examination, and further even a production plan and production management.
It is very useful to introduce the network computing, in this way, with respect to the operations that are to be performed under a common object or common circumstances, especially, with respect to the processing form in which the cooperative operations are needed between a plurality of equipment pieces. In this view, even in case of the automobiles, the added value and function of which have yearly been increased, there has been demanded a system that unitarily controls and manages respective electrified units, which have been electronically controlled, through a network. Especially, the introduction of a CAN (Controller Area Network) that is an on-vehicle LAN standard has proceeded.
The CAN is a protocol that has been internationally standardized as an ISO 11898. It adopts a serial communication system that replaces a differential voltage between two lines called xe2x80x9cCAN busesxe2x80x9d with a digital value of 0/1 and that uses the resulting signal as a transmission and reception signal. It therefore has a high resistance to noise and makes it possible to set its transmission rate up to 1 Mbps at maximum. It therefore characteristically enables a very highly reliable and highly speedy network control to be performed even when compared to the conventional communication system.
Ordinarily, a CAN controller is loaded on each of the above-described respective electrified units (each hereinafter called xe2x80x9ca CAN nodexe2x80x9d) that have been connected to the CAN buses. The data transmission and reception between the CAN nodes that are made through the use of the CAN buses as an intermediary can be performed with this CAN controller. Especially, the CAN controller characteristically has an abnormality detecting function on the network and a re-synchronizing function thereon to thereby achieve the stabilization of the communication.
Further, the CAN is a bus system that has multi master ability. Therefore, every CAN node can transmit data onto the CAN buses and a plurality of CAN nodes can receive the signal on the CAN buses simultaneously. In this CAN network, it is not necessary, in principle, to set a so-called xe2x80x9capparatus addressxe2x80x9d (xe2x80x9cstation IDxe2x80x9d). Instead, the content of the message is represented by an ID (a message ID) that has been added to each piece of message data to be transmitted.
This message ID is also referred to when determining the priority when bus accesses from a plurality of CAN nodes have competed. Only the message from the CAN node that has won a victory out of the communication mediation as a result of the line scramble appears on the buses. And the CAN controller that has been loaded on each CAN node determines according to this message ID whether or not the message should be formally taken in.
Ordinarily, the CAN controller is supplied in the form of a chip so as to exhibit the function that has been included therein in accordance with the CAN protocol. It therefore serves as an interface between the CPU that is loaded on the CAN node and the CAN buses. Further, by making this CAN controller into a module, the CAN controller is also supplied in actuality in the form of a one-chip microcomputer having the CAN controller built-in.
The CAN is originally developed for the purpose of being used in an automobile as mentioned above. However, by taking advantage of the characterizing features thereof that the amount of wiring is reduced; the weight and cost are resultantly reduced; the real-time performance is high; and the strength against the electrical interference is high, the CAN is also adopted in the built-up of the above-described FA, medical equipments, or ships.
In the above-explained CAN controller or one-chip microcomputer (hereinafter called xe2x80x9ca CAN chipxe2x80x9d) having the CAN controller built-in, the signal is delayed due to the signal processing circuits disposed between the CRX terminal that receives a serial signal from the CAN buses and the CAN module that is actually exhibitive of various kinds of their functions that have been included therein in accordance with the CAN protocol. Therefore, the signal that is received by the CAN module is delayed with respect to the signal received in the CAN buses. In addition, there is a delay that occurs due to the transmission cable from the transmission node to the reception node. The above-described re-synchronizing function operates in order to compensate for these signal propagation delays.
However, in the manufacturing process of the above-described CAN chip, when testing the operation of the CAN module section, the above-described delay in the signal propagation fluctuates depending on the testing conditions such as the environmental temperature and the applied voltage, and, according to each of these fluctuations, the re-synchronizing function is inconveniently executed. Therefore, there is the problem that the stable and speedy test in a stationary state of synchronization was inconveniently hindered.
This problem involves therein the possibility that, especially, with respect to a normal CAN chip, the test result indicating that a CAN chip is defective may inconveniently be output even in a case where a serial testing signal is input to an input terminal (hereinafter called xe2x80x9ca CRX terminalxe2x80x9d) having a serial signal input thereto from the CAN buses with a timing that is determined on a basis of, for example, an internal clock signal.
It is indeed possible to prepare test vectors for each fluctuating testing condition and repeat a test that corresponds to each of such test vectors. However, such test vectors become huge in number. On the other hand, it is difficult to predict or estimate the fluctuation of the testing conditions. Therefore, this solution is not a realistic one.
The above-described problem will be explained with reference to the drawing. FIGS. 5A and 5B are explanatory views illustrating the occurrences of a bit timing in the conventional CAN controller. Especially, FIG. 5A illustrates the exhibition of the re-synchronizing function with respect to first testing conditions while FIG. 5B illustrates the exhibition of the re-synchronizing function with respect to second testing conditions.
In the CAN, a length of time that is called xe2x80x9ca bit timexe2x80x9d is allotted to each of the respective bits that constitute the above-described message (message frame). This bit time is constructed of four segments of a Synchronization Segment (hereinafter called xe2x80x9cSyncSegxe2x80x9d), a Propagation Segment (hereinafter called xe2x80x9cPrSegxe2x80x9d), a Phase Segment 1 (hereinafter called xe2x80x9cPhSeg1xe2x80x9d), and a Phase Segment 2 (hereinafter called xe2x80x9cPhSeg2xe2x80x9d). Further, each segment is constructed of a prescribed number of time-dividing units. This time-dividing unit is hereinafter represented by Tq (Time quantum).
It is to be noted that 1 Tq is produced by a clock that is given from outside the CAN chip and in the specification of the CAN protocol it is defined that SyncSeg=1 Tq.
In the bit time illustrated in FIGS. 5A and 5B, it is set that PrSeg=3 Tq, PhSeg1=2 Tq, and PhSeg2=2 Tq, whereby illustration is made of a case where each bit, i.e., 1 bit is constructed of the sum total of 8 Tqs that is composed of these 7 Tqs plus 1 Tq that is SyncSeg.
In a case where the bit edge of a serial signal (hereinafter called xe2x80x9ca CRX inputxe2x80x9d) that is input from a CRX terminal is detected within the SyncSeg time period, or a time period (the Tq [P2] of PrSeg in FIG. 5A) that is prepared by adding a SJW (Synchronization Jump Width) that is set as 1 Tq to this SyncSeg, namely, in a case where an ideal bit edge containing no delay therein is detected, synchronization is started determining the Tq corresponding to the location of this bit edge as SyncSeg. Thereafter, the value that is indicated by the CRX input at a point in time when 3 Tqs of PrSeg plus 2 Tqs of PhSeg1 have elapsed, i.e., at a bordering point in time ([Sampling Point] in the figure) between the PhSeg1 and the PhSeg2 is procured as bit data.
Also, in a case where, as illustrated in FIG. 5A, because of the delay of the CRX input under the first testing conditions, the bit edge of the CRX input is detected during the Tq [P1] of the PrSeg that immediately succeeds the time period that consists of the SyncSeg and the SJW added thereto, namely, in a case where an internal delay D1 has occurred, the re-synchronizing function of the CAN controller automatically works. As a result, a Tq next to the Tq [P1] of the PrSeg corresponding to the location of the detected bit edge is newly set as the starting Tq [P2] of the PrSeg, whereby the synchronization is made to persist.
Namely, as a result of this, re-synchronization is achieved. And the value that is indicated by the CRX input at the Sampling Point that thereafter comes is procured as bit data. Accordingly, in this case, the result is that the PreSeg is prolonged by 2 Tq from the initial SyncSeg.
Next, in a case where, as illustrated in FIG. 5B, because of the delay of the CRX input under the second testing conditions, the bit edge of the CRX input is detected during the Tq [P0] of the PrSeg that immediately succeeds the time period that consists of the SyncSeg and the SJW added thereto, namely, in a case where an internal delay D2 has occurred, also, as in the case of the above, by the re-synchronizing function of the CAN controller, a Tq next to the Tq [P0] of the PrSeg is newly set as the starting Tq [P2] of the PrSeg, whereby re-synchronization is achieved. Accordingly, in this case, the result is that the PreSeg is prolonged by 3 Tq from the initial SyncSeg.
In the FIGS. 5A and 5B explained above, depending on the testing conditions, a difference in the internal delays occur under the respective testing conditions. Resultantly, through the performance of the re-synchronizing function, a delay difference DE that is the difference portion between these internal delays appears as the difference in the prolonged amount of Tq between these internal delays.
In the actual use form of the CAN controller, the execution of the re-synchronizing function due to such internal delays is indeed effective as a performance of enhancing the reliability on the communication. However, as stated above, while testing a CAN chip, the above-described change in state of synchronization of the CRX input is inconveniently observed as a delay of the Ack signal transmission or the error flag. This inconveniently hinders the execution of the test. Further, the shorter the time quantum Tq becomes, namely, the more speedily the test is executed, the greater the adverse effect of the delay becomes relatively. Therefore, the stable execution of the test becomes difficult.
The present invention is made in order to solve the above-described problems. It is an object of this invention to provide a CAN controller and a one-chip computer having the CAN controller built-in, which during testing enable the test to be performed with a high speed and stably without being influenced by the execution of the re-synchronizing function.
According to this invention, there is provided the control unit that can control whether or not the edge detection signal of the serial signal that is detected by the edge detection unit is to be input to the re-synchronization unit for causing a re-synchronizing function prepared in accordance with a CAN protocol to be executed. Therefore, it is possible to make ineffective the re-synchronizing function performed by the re-synchronization unit according to the input of the control signal that performs this control operation.
According to this invention, when the control unit inputs the control signal indicating a test mode, the edge detection signal that is output from the edge detection unit is not output to the re-synchronization unit. Therefore, when performing the operation test of the CAN controller, it is possible to make the re-synchronizing function ineffective.
According to this invention, the control unit is constructed of only one AND gate and only one inverter. Therefore, it is possible to simplify the circuit construction.
According to this invention, there is provided between the CAN module and the signal processing circuit for performing various processing such as elimination of noises with respect to the serial signal input via the CAN buses the selecting unit that inputs the signal (first signal) that is output from the signal processing unit and the serial signal (second signal) that has bypassed the signal processing circuit, and that inputs to the CAN module either one of the first signal and the second signal. It is therefore possible to select the serial signal input to the CAN module according to the input of the control signal for performing such selection.
According to this invention, when the selecting unit inputs the control signal indicating a test mode, the selecting unit can input the serial signal that does not pass through the signal processing unit, directly from the CRX terminal. Therefore, when performing the operation test of the CAN controller, it is possible to decrease the propagation delay of the serial signal that is caused to occur due to the signal processing unit.
According to this invention, the selecting unit is constructed of only one inverter and only two clocked inverters. It is therefore possible to simplify the circuit construction.
According to this invention, even when propagation delay has occurred during a time period that lapses until the serial signal that has input from the CRX terminal actually reaches the CAN module, if the frequency of the second clock signal is small enough to absorb this propagation delay, it is possible, by selecting this clock, to prevent the change in the propagation delay that occurs depending on the testing conditions from having an effect on the CAN module.
According to this invention, when the clock switching unit inputs the control signal indicating a test mode, the serial signal that is input from the CRX terminal is synchronized according to the second clock signal whose frequency is smaller than that of the first clock signal that is used in the ordinary operation, and this serial signal is transmitted to the CAN module. Therefore, it is possible to prevent the propagation delay from having an effect on the CAN module.
According to this invention, the selecting unit is constructed only of one inverter, two clocked inverters, and one D flip flop. Therefore, it is possible to simplify the 1S circuit construction.
According to this invention, there is provided the internal communication unit that, between at least two CAN modules of the plurality of CAN modules, generates signals corresponding to serial signals input from a CAN bus on the basis of the serial signals that are output from the respective CAN modules to the CAN bus, and that inputs the generated signal to the respective CAN modules as the serial signal that is input from the CAN buses. Therefore, it is possible to perform the communication between the CAN modules in the interior of the CAN controller without using the CAN buses as an intermediary.
According to this invention, when the internal communication unit inputs the control signal which indicates a testmode, it is possible to perform the communication between the CAN modules in the interior of the CAN controller without using the CAN buses as an intermediary. Therefore, when performing the operation test of the CAN controller, it is possible, in place of the serial signal that is input from the CAN buses in the ordinary operation, to input the signal that is generated according to the respective serial signals output from the respective CAN modules, to these respective CAN modules.
According to this invention, the internal communication unit is only constructed of one NAND gate, one inverter, and three-state buffer. Therefore, it is possible to simplify the circuit construction. Simultaneously, it is possible, with respect to the CAN controller whose dominant level based on the CAN protocol is set as a logical level of xe2x80x9cLxe2x80x9d, to perform the communication between the CAN modules inside this CAN controller according to the control signal.
According to this invention, the internal communication unit is only constructed of one NOR gate, one inverter, and three-state buffer. Therefore, it is possible to simplify the circuit construction. Simultaneously, it is possible, with respect to the CAN controller whose dominant level based on the CAN protocol is set as a logical level of xe2x80x9cHxe2x80x9d, to perform the communication between the CAN modules inside this CAN controller according to the control signal.
According to this invention, in the one-chip computer that has built-in the CAN controller according to any one of above inventions added as an on-chip form, also, the function that is brought about by this CAN controller can be given.